Reverse DDS (RDDS) Phase Lock Loop System for OCXOs

 

This page is mainly for visitors to my web pages whom may not take Scatterpoint.  It is intended to complement the G4NNS Scatterpoint Articles Parts One and Two, February & March 2010. This page should also be read in conjunction with the G4NNS web page.  The intention is this RDDS project will be found useful to improve frequency stability in existing amateur microwave systems, especially for existing beacons, as well as for consideration in the planning of new microwave signal source schemes.

 

Two methods are principally used today in new designs to produce stable amateur microwave signals for beacons or local oscillators.  Either the well established OCXO, generally in the 95-135 MHz region or more recently by the use of DDS ( Direct Digital Synthesis ) integrated circuits.   Is DDS the best way forward and if so how should it be implemented ?

 

The free running OCXO often has its ageing limitations for longer term 24/7 stability.  The crystals supplied at reasonable amateur prices today, except for a very few manufactures seem to have noticeably declined in performance over the last ten years, both in ageing characteristics and frequency jitter.  This may well be because most crystals are now produced for digital clocks and not for use as analogue signal sources.  We amateurs have also improved our systems and expectations in the meantime to recognise the limitations in the crystal products available.  So what should we consider to be the right microwave approach to improve our existing and future beacon and station equipments.  The digital approach with perhaps a DDS used conventionally as an OCXO replacement may well have poorer phase noise performance at microwave frequencies and ‘sprogs’ needing removal so as not to be an ‘in band’ nuisance to those living in the shadow of a local beacon or when strong signals are encountered when it is used as a receiver local oscillator.  Note the DDS is dependant for performance on its Reference or Clock quality and also the magnitude of the clock multiplier settings inside.

 

A phase lock loop has become essential for new Amateur Communication Systems to ensure signal sources remain on the intended frequency.  Receivers rarely use oddball crystal frequencies so PLL circuitry such as the CT1DMK method using a CPLD IC will often suffice, however for oddball frequencies used for example in beacons the long established WA6CGR PLL is very good but uses hard to find TTL dividers.  These PLL systems will discipline your signal origination source but problems may exist with huge un-manageable frequency divisions degrading the locking performance.  In the case of FSK beacon ident the chirp produced on the frequency shift may also be quite bad.  So what of DDS signal production.  The writer of this page has only limited DDS experience but the significant problem appears to be the ‘sprog’ and ‘phase noise’ levels produced when used as a prime source multiplied to our usual high frequencies.  Only a limited amount of experimentation has been done by G8ACE but it seems to indicate a crystal filter is almost mandatory following a DDS source for microwaves. Generally the signal must also be produced at half our usual OCXO frequencies due to maximum clock rates which will have further implications on the phase noise for microwave signals.  The G4NNS web page shows a comparison between an RDDS produced signal and DDS signal.  Particularly note the noise floor level differences.

 

So what is RDDS (Reverse Direct Digital Synthesis).   Reverse DDS means using the existing OCXO source as before as the beacon prime frequency source but is now additionally used as the clock in the added RDDS PLL hardware.  A DDS IC usually uses the reference clock ( plus optional multiplier ) signal to produce the output signal with limitations on the maximum output frequency obtainable. With the Reverse DDS the output signal is lower in frequency and so no clock multiplier is required and the principle constraint is that the OCXO input frequency is within the chosen DDS IC maximum input clock rate.  180 MHz for the AD9851 IC.  The RDDS is loaded with Hex numbers from the PIC IC to convert the input OCXO clock to the PLL reference frequency.  The reference signal in the PLL may be an oddball frequency as long as its stable but with the constraint it may not be easily further lockable to GPS for further improved stability.  When FSK keying of the signal is required the PIC sends new numbers to the DDS chip changing the output frequency.  G4NNS has done considerable work on the RDDS PIC software initially developed by G4JNT.  Visit the G4NNS website for all the current RDDS software information for this particular project.

 

Whilst this newer DDS concept to improve our microwave source stability has existed for sometime from the work by G4JNT an easily constructible module to do the job did not.  So an attempt has been made here to produce a project which either can be built as described to do the required PLL function as outlined, requiring little understanding as to the inner workings but with an ability to build an smd project . Or it can be developed with new software by the individual constructor.  Again see G4NNS as to how the PIC I/O might be used.

 

The choice of which DDS IC was to be used was fairly easy.  The AD9851 is a standard 28 pin IC with 0.65mm spaced lead outs on two sides which can be carefully soldered into a manufactured PCB with solder resist by an experienced smd constructor.  The AD9852 IC has lead outs on four sides plus a heat dissipation pad underneath which needs to be soldered down effectively and was considered to be an ‘iffy job’ as its not visible and a none starter for home produced beta PCBs where plated through holes are needed to conduct the heat away to a heat dissipater pad on the opposite side of the PCB. 

 

So what are the plus and minus considerations of available ICs.  Using the AD9851 means that constructional success is pretty much assured ( by the competent smd constructor ).  The limitation of using the AD9851 is the frequency step size on the output frequency and is perhaps limited to around 50 Hz frequency steps at 10 GHz.  The reference frequency used also affects frequency step size so it should be considered in design but the resulting frequency obtained is considered in any event to be at least as accurate as the average IF transceiver frequency readout allows.  The overwhelming advantage of RDDS is of course the stability obtained rather than absolute accuracy and the ability to retro fit to existing OCXO systems.  The AD9852 whilst enabling much finer frequency resolution ( therefore accuracy ) is considered to be just too difficult to install properly mechanically and for thermal reliability in the amateur environment.

 

The RDDS PCB was designed to fit within a standard available tin plate box, 55 x 110 x 30mm deep being chosen.  Note when installing this PCB to the box it has cut away opposite corners to fit around the internal box seams. PCB orientation is therefore important.  RF connections are at one end of the box with top and bottom PCB board separation between OCXO signal ( clock ) and Reference.  This is to minimise possible Reference signal cross talk into the OCXO  and therefore into the output signal.  Two feed through capacitors are supplied as standard for fitting to the opposite end of the box on the component side ( bottom ) for dc input and OCXO dc control output.  Space at the same end but at the top side of the PCB is available for feed through insulators to carry additional PIC I/O signals.  Alternatively the box end can be cut away to allow entry of a  20 way ribbon cable for extensive IO signals to and from the optional 20 way connector.  As use of these additional PIC I/O signals are at the discretion of the experienced constructor the connector parts do not form part of the basic kit components.

 

The OCXO signal loops through the box for obtaining RDDS input clock and uses two sma connectors, although one sma could be used with tee piece adapter.  It is very important that the OCXO loop through signal is properly terminated at its final destination otherwise the RDDS PCB input circuitry may be compromised by standing waves causing a minima in signal level right where it is needed in the RDDS.  An optional test point position is available on the PCB layout for measuring RDDS input signal amplitude  following the OCXO buffer amplifier.  A second test point installation point is available at the RDDS output to monitor the RDDS generated reference signal for the PLL comparator IC.   A third test point position allows monitoring of the reference signal level applied to the comparator.  Comparitor input signal levels ( RDDS & Ref ) should be of the order 300 mV pp measured with a suitable oscilloscope.  For standard references, eg.  5 and 10 MHz OCXOs that G4NNS and G8ACE have used then the on PCB attenuator components will be satisfactory.  The PCB has the facility to accommodate a reference level input trimmer capacitor rather than resistor allowing variable setting of reference signal level and also an optional tuned circuit to allow clean up of distorted reference signals.  Sine wave signals applied to the comparator IC, NE602 (SA602) are to be preferred.  A good oscilloscope will show the output of the DDS at the reference frequency as a stepped waveform constructed from the OCXO clock.  Clean up of this stepped signal at the RDDS output was not found to be necessary.

 

A panel meter is quite a valuable aid to show the OCXO varicap control voltage and therefore crystal ageing shift and time to next OCXO retune for poor OCXO crystals in a beacon situation.  PCB accommodation is available for a resistive attenuator so a meter can be connected to monitor this varicap control voltage.    Comprehensive PCB connection points are available for PIC I/O in the form of an optional 20 pin connector ( can also used for handbag links for Rx LO frequency selection )  and an optional PICKIT connector for those whom wish to develop special applications.  Note the handbag or hard wired PCB link for disconnecting the on board PCB 5v when PICKIT development is in use.  Also of significant importance is the RS232 connection point for easy programming of the RDDS, as developed by G4JNT.  G4NNS has documented the use of this and difficulties with some RS232 PC connections via USB when attempting to use this useful port.

 

Whilst the assumption is for F1 inbuilt keying, as this is the norm for most existing beacons, the PIC controller will of course source an I/O signal to enable A1 keying.  Its all a matter of interfaces with the I/O.  If you wish to keep your existing external F1 keyer than its just a matter of again interfacing with the I/O.

 

A total of three initial prototype PCBs were created by G8ACE before the final production PCB version was sent to the PCB manufacturer.  The second two home produced PCB being duplicated and built by G4NNs whom then used these to develop the software.  The manufactured final version of the PCB takes typically less than three hours to populate with components and box by both G4NNS and G8ACE.  The initial batch of  15 PCBs have been distributed largely for beacon stability improvements.  Results so far from independent constructors look promising.  A second batch of kits is currently being created to be available at RAL.  If you have an interest in a kit then please make it known at RAL, April 17th 2010.  It is hoped a demonstration beacon Tx will be running for interested persons to examine.

If you wish to register an interest in a kit, email me, G8ACE at this address:  kits at dsl dot pipex dot com  and place RDDS into the Subject line. 

 

Module Graphics here.

 

* Notes:

·        The Bell Hill 24 GHz  (24048.905 MHz) beacon has been using the WA6CGR PLL for a considerable time, builder G8BKE.  Other beacons at Bell Hill are locked by G4JNT systems.

·        The Bell Hill 47 GHz (47088.905 MHz) beacon uses the CT1DMK PLL as does the GB3FNM 47 GHz (47088.92) MHz) beacon, both built by G8ACE.  Note all three of these beacons above use offsets of the Reference OCXO to achieve the required transmit frequency.  This makes GPS lock extremely difficult. Using RDDS would overcome this problem as the reference standard may remain correctly on frequency.

·        GB3FNM  6cm (5760.92 MHz)  and 24GHz (24048.92 MHz) beacons are now locked by RDDS to a 5MHz standard.

·        GB3LEX  3cm (10368.955 MHz) beacon is now locked by RDDS to a reference frequency standard.

 

Link to G4NNS applications web page.

 

G8ACE March 2010

 

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